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Computer Science IGCSEPDF 24
142 pagesrevision 46930
PDF 24
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retrieved from memory.
This address is transferred to the memory address register
(MAR).
The address is then transmitted via the address bus, where it
waits for a control signal to proceed.
A signal is issued along the control bus by the control unit
(CU) to communicate with main memory.
Once the signal is received, the corresponding instruction or
data is retrieved from memory and sent to the memory data
register (MDR) through the data bus.
A duplicate of the fetched instruction or data is then stored
in the current instruction register (CIR) for processing.
Finally, the program counter (PC) is incremented by 1, so it
points to the subsequent instruction to be fetched in the next
cycle.
DecodeStage
During the decode stage of the cycle, the CPU interprets the
fetched instruction to determine what action is required.
This involves dividing the instruction into two main
components:
Opcode – specifies the operation to be performed
Operand – indicates the data to be used or the memory
location where the data can be found
→ The operand can represent either a direct piece of data
or an address
Execute Stage
During the execute stage, the CPU performs the action
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